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Company: Larsen & Toubro
Location: Stratford
Posted on: February 19, 2021

Job Description:

You will be responsible for leading hierarchical DFT implementation for a next-generation SoC project.
Your responsibilities also include: --- Define & document DFT requirements/Specifications for IP/Block and Chip level --- Execute DFT Lint to identify scan DRC violations and resolution --- Top level and hard macro block level scan insertion with high EDT compression ratio (Hybrid LBIST, EDT IP/ATPG, LPCT EDT, AC scan verification with high speed PLL, MBIST, and IJTAG) --- Plan and Insert MBIST and memory repair (BISR) at RTL --- Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests --- ATPG pattern verification on pre/post-route gate-level netlist including 0-delay and SDF --- Work with backend team for the MBIST/Scan mode constraints generation, scan reorder, VCDs for IR drop analysis during DFT, ECO changes and formal verification (LEC), and timing closure --- Support test engineer for pattern generation, tester debug and failure analysis. --- Work with Test Engineering team during Silicon bring-up and creating flow/scripts necessary for debugging/diagnosing compression LPC ATPG patterns (stuck-at/at speed), MBIST patterns on ATE for development and production programs --- Expert knowledge of Mentor Tessent toolchain
Required Qualifications: --- Hands-on hierarchical DFT flow experience from RTL to netlist --- Strong knowledge and experience with both JTAG (IEEE1149.1) and IJTAG (1687) --- Experience in inserting EDT, wrapper cells and OCC --- Experience in analyzing DFT DRC violations and fault coverage analysis --- Expertise in ATPG. Debug and resolve ATPG DRC and chain trace issues --- Gate level simulations and debug; both 0-delay and with SDF DFT --- Expertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementation --- Experience in debugging tester/ATE failures, silicon bring-up and yield and test time improvement --- Experience in Perl/TCL scripting and good verbal/written communication skills --- 7+ years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success

Keywords: Larsen & Toubro, Visalia , DFT LEAD, Other , Stratford, California

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